A conventional tristate BICMOS TTL output buffer circuit is illustrated in FIG. 1. The example of FIG. 1 is an inverting output buffer circuit delivering low and high potential level output signals at the output V.sub.OUT in response to high and low potential level data signals at the input V.sub.IN. The output pullup and pulldown transistors are bipolar transistors. The pullup Darlington transistor pair Q3,Q4 sources current to the output V.sub.OUT from an output high potential power rail V.sub.CCI through Schottky diode SD9. The pulldown transistor Q5 provided by high current drive parallel transistor elements Q5A,Q5B sinks current from the output V.sub.OUT to the low potential power rail GNDO. The bipolar phase splitter transistor Q2 controls the conducting states of the respective pullup and pulldown transistors in opposite phase in response to data signals at the input V.sub.IN. The input V.sub.IN is coupled to the base node of phase splitter transistor Q2 through input Schottky diode SD4.
With a high potential level signal at the input V.sub.IN phase splitter transistor Q2 is conducting and turns on the pulldown transistor Q5. Discharge current from the output V.sub.OUT assists in the turn on of the pulldown transistor Q5 through an accelerating feedback circuit provided by bipolar feedback transistor Q1 having a base node coupled to the input high potential power rail V.sub.CCI through resistor R3. The input and output high potential power rails V.sub.CCI, V.sub.CCO may be relatively isolated from each other for noise reduction by, for example, a split lead leadframe or by separate supply rails and pins. The phase splitter transistor Q2 is coupled to the input high potential power rail V.sub.CCI through collector resistor R1. It discharges the base and turns off pullup transistor Q3. Alternative discharge paths through Schottky diode SD1 and through resistor R2 and Schottky diode SD6 accelerate turn off of pullup transistor Q4.
With a low potential level data signal at the input V.sub.IN the phase splitter transistor Q2 turns off and the base of the pulldown transistor Q5 is discharged through resistor R4. To prevent turn on of pulldown transistor Q5 by capacitive feedback Miller current during charging of load capacitance and transition from low to high potential level at the output V.sub.OUT, an AC Miller killer circuit (ACMK) Q6,SD5,D1,SD1 is coupled to the base node of pulldown transistor elements Q5A,Q5B. The ACMK discharging parasitic base drive feedback Miller current to the low potential power rail GNDO.
A tristate circuit for implementing an inactive high impedance tristate condition at the output V.sub.OUT is provided by CMOS transistors P1,P2,P4,N2 having control gate nodes coupled to tristate enable input OE. For the active bistate mode of operation at the output V.sub.OUT, a low potential level OE signal turns on the tristate PMOS transistors P1,P2,P4. The tristate PMOS transistors provide low impedance coupling of the input high potential power rail V.sub.CCI to the input, phase splitter and feedback circuits. Tristate NMOS transistor N2 is also coupled to the tristate enable input OE. With the low potential level OE signal, tristate NMOS transistor N2 is non-conducting blocking the path to low potential power rail GNDO from the base node of output pulldown transistor Q5 for active operation in the bistate mode.
The tristate enable circuitry also incorporates Schottky diodes SD2,SD3 coupled between the respective base nodes of pullup transistor Q3 and feedback transistor Q1, and a complementary tristate enable input OEB. With a high potential level OEB signal, this path is blocked for bistate operation at the output V.sub.OUT in the active mode.
The tristate circuitry disables the output V.sub.OUT in a high impedance third state with tristate enable high potential OE signal and low potential OEB signal. The high potential level OE signal turns off tristate PMOS transistors P1,P2, and P4 isolating the input, phase splitter and feedback circuits from the high potential power rail V.sub.CCI. Tristate NMOS transistor N2 turns on and disables the bipolar pulldown transistor Q5. The low potential level OEB signal disables the bipolar pullup transistors Q3,Q4 as well as the bipolar feedback transistor Q1 through Schottky diode paths SD2,SD3.
A disadvantage of the tristate BICMOS TTL output buffer circuit of FIG. 1 is the high power dissipation during active operation in the bistate mode. With a low potential level data signal at the input V.sub.IN holding off the phase splitter transistor Q2, a steady state or quiescent input current I.sub.CC continues to flow from the high potential power rail V.sub.CCI through tristate transistor P1, resistor R5 and input diode SD4 to the input node V.sub.IN. This quiescent current continues for the duration of a low potential level signal at the input V.sub.IN.
It should also be noted in the conventional BICMOS TTL output buffer circuit of FIG. 1 that CMOS transistors are introduced in the essentially bipolar TTL output buffer circuit only in the tristate enable circuit The CMOS transistors P1,P2,P4,N2 are limited to the power circuit paths for connecting or disconnecting the bipolar output buffer circuit elements with respect to the high and low potential power rails. The tristate CMOS transistors P1,P2,P4,N2 are controlled only by power signals at the tristate enable circuit input OE, and are not incorporated into the data path.
In the previous technology of bipolar tristate output buffer circuits, dual bipolar phase splitters have been used to reduce power dissipation. For example the Steven N. Goodspeed U.S. Pat. No. 4,287,433 describes a TRANSISTOR LOGIC TRISTATE OUTPUT WITH REDUCED POWER DISSIPATION with an all bipolar tristate enable circuit. This circuit reduces power dissipation, however, in an entirely different context power. Dissipation through the all bipolar tristate enable circuit is reduced during the inactive tristate mode of operation.
Dual bipolar phase splitter transistors are also described in the Paul J. Griffith U.S. Pat. No. 4,255,670 for a TRANSISTOR LOGIC TRISTATE OUTPUT WITH FEEDBACK. In this circuit the second phase splitter transistor is used to define an accelerating feedback circuit from the output to the base of the pulldown transistor without connection to the tristate enable circuit. The bipolar enable gate is therefore separated from the output. Furthermore in these two U.S. Pat. references the concept and context of dual phase splitter transistor circuits is limited entirely to all bipolar transistor output buffer circuits.